The present invention relates to an information communication equipment, particularly to a speech path switch in which a so-called asynchronous transfer mode (ATM) exchange performs a switching operation by use of a fixed-length packet which is composed of an information or data portion including communication information and a header portion including routing information. The present invention relates more particularly to a multi-stage link switch which is suitable for realization of a large scale switch by the combination of a plurality of switch elements.
In order, to construct a large scale speech path switch, a multi-stage link switch is often used in which switch elements each having a certain scale are multistage connected. One article relevant to such a technique is "STUDIES OF LARGE SCALE INTEGRATION OF ATM SWITCH", Electronics, Information and Communication Engineers of Japan, Proceedings B-198 of Autumn National Congress, 1989.
In general, a multi-stage link switch employs a system in which the number of internal links or the internal link speed or rate is increased in order to reduce internal blocking. For example, as shown in FIG. 2, m-incoming/r-outgoing (m.times.r) switch elements generating switching operation between m incoming lines connected to m incoming highways of the link switch and r (m&lt;r) outgoing lines, m-incoming/m-outgoing (m.times.m) switch elements generating switching operation between m incoming lines and m outgoing lines and r-incoming/m-outgoing (r.times.m) switch switching elements generating a switching operation between r incoming lines and m outgoing lines connected to m outgoing highways of the link switch are connected in a three-stage configuration so as to form an m.sup.2 -incoming/m.sup.2 -outgoing (m.sup.2 /m.sup.2) switch which has m.sup.2 incoming highways and m.sup.2 outgoing highways and in which the internal link is extended.
Further, in an ATM switch in which the statistical multiplexing of fixed-length packets is performed and in which the internal link rate is increased to nv corresponding to n times higher than the incoming/outgoing highway rate v, prevents blocking which is caused by a fractional line effect. The number of internal links and the internal link rate are complementary to each other, and hence an equivalent effect can be obtained from either one or both of the number of internal links and the internal link rate.
The condition of non-blocking of a speech path switch in the ATM exchange or numerical values for the non-blocking are described in details by U.S. Pat. No. 4,910,731 to the present inventors issued on May 20, 1990.
An example of applications of the above non-blocking condition is shown in FIG. 3. In the shown three-stage link switch, no blocking occurs for an input call having the rate of the source of the call up to v/3, wherein v is the incoming/outgoing highway rate.
One of configurations of a switch element of the speech path switch in the ATM exchange is known a shared buffer memory type switch element which is described by, for example, the U.S. Pat. No. 4,910,731 referred to in the above. This type of switch element is suitable for large scale integration since the memory utilization efficiency is high.
However, in the case where a multi-stage link switch as shown in, for example, FIG. 3, is constructed by use of the shared buffer memory type switch elements, three kinds of switch elements including an m-incoming/3m-outgoing (m.times.3m) element an m-incoming/m-outgoing (m.times.m) element and a 3m-incoming/m-outgoing (3m.times.m) element, m being an integer are required. An ideal condition is to integrate the switch elements on one chip. In the above case, however, three different kinds of LSI's are necessary. This problem exists not only in the case where the shared buffer memory type switch elements are used but also in the case where the other type switch elements are used.
Also, there is a problem that the last stage of the multi-stage link switch has a complicated construction because it requires a concentration function.